This invention relates to the fabrication of three-dimensional electronic packages in which a multiplicity of individual integrated circuit (IC) chips are secured together in a stack which provides a very high density electronic package.
The assignee of this application pioneered the use of IC chip stacks, first as modules providing photo-detector focal plane circuitry, and then as units suitable for computer memories and the like. U.S. Pat. Nos. 4,525,921 and 4,646,128 relate to the stacks designed for general use as memory devices and other non-focal-plane packages.
The methods used for fabricating such three dimensional (3D) IC chip stacks have become increasingly sophisticated. The three dimensional approach has been applied to both SRAM and DRAM memory chips with satisfactory results. Stacking of memory chips has reached density levels of seventy chips in a 0.220 inch.times.0.520 inch.times.0.520 inch stack, each chip having a 1 megabit memory. Expectations are to increase the memory per chip and the number of chips per stack.
In this approach chips are tested, measured, and then assembled in a stacking fixture, with a thin layer of adhesive between adjacent chips. The stacked chips and fixture are then placed in an oven and baked at the curing temperature for a given time. The "face" of the stack is then etched to expose the thin film metal leads. The leads are of the order of 1 micrometer thick and 125 micrometers wide. After sufficient etching, several layers of passivation, preferably polyimide, are deposited over the stack face, covering to a depth somewhat greater than the length of the exposed thin film metal leads. This polyimide serves as an insulating layer between the silicon chips and the metal pads and/or buslines deposited later in the process. After curing the polyimide layers, the face of the stack is thinly lapped to clear cured polyimide from the thin film metal lead ends.
Using photolithography and vacuum deposition of Ti-W/Au or other suitable metal or metal combination, pads and buslines are formed on the stack face. The pad to metal lead interconnect that is formed is referred to as a "T-connect". Such a T-connect is depicted in FIG. 1. To complete the assembly, the stack can be solder bumped or wire bonded to a substrate for eventual connection to external circuitry. One of these assemblies is shown in common assignee U.S. Pat. No. 4,706,166.
Since memory chip wafers are usually selected "off the shelf", and therefore not dedicated to the stacking process, some modification is required before the die can be used for this purpose. Depending upon how the finished stack is to be attached to its substrate or circuit assembly, it has been found to be appropriate to reroute the pads by thin film metal leads to one edge of the "new" chip. For some applications, however, it may be preferable to reroute to more than one edge of the chip. This wafer lead rerouting process is disclosed in common assignee U.S. Pat. No. 5,104,820.
One of the possible chip stacking processes is disclosed in common assignee U.S. Pat. No. 4,617,160. After a stack has been fabricated, there are several process steps performed on the access plane of the full stack. It is economically no more costly to perform these process steps on a stack containing 70 chips than on a stack containing 10 chips. In fact, it is easier to work with a larger stack because it is easier to handle. These process steps performed on the full stack include those steps discussed above and in U.S. Pat. No. 4,525,921.